Three day workshop on “ASIC Design”

MAEER’s Maharashtra Institute of Technology, Kothrud, Pune-38 Department of Electronics & Telecommunication Engg. in association with CoreEL technologies hosted a three day workshop on “ASIC Design” for M.E (Electronics and E&TC) students and staff under Savitribai Phule Pune University from 31st Aug to 2nd September 2016. On 1st Sept. “Hands on” for Mentor Graphics software by CoreEL technologies was arranged as a part of the workshop. Under the able guidance of Prof. Dr. P. D. Khandekar Vice-Principal, MIT, Pune, invited speakers for the workshop were: 1. Dr. Dipankar Nagchoudhuri, Retired Professor, DAIICT, Gandhinagar 2. Mr. H. S. Jatana, Divisional Head VLSI, Semiconductor Lab, ISRO, Chandigarh 3. Dr. M. B. Mali, Head, E&TC Department, SCOE, Pune 4. Prof. Ketan Raut, Associate Professor, VIIT, Pune In the “Hands on” of Mentor Graphics Pyxis tool, topics covered are as follows: • Create NAND Gate schematic using pyxis schematic tool • Simulation of Nand Gate using GDK130nm pdk • Analyze the waveform in EZwave and apply different function using Measurment tool • Draw a Nand Gate layout using Pyxis layout tool • Perform physical verification using Calibre tool • Perform parasitic extraction and do post layout simulation ASIC Design workshop has given insight on Signal Integrity Issues, CMOS Digital Circuit Design, Demonstration of ASIC Design , Ultra Low Voltage Analog Integrated Circuits and Simulation, CMOS Analog Design. This workshop was very helpful for faculty of Engineering Institutes and researchers. Participants had great interactions with the resource persons. Coordinator: Mrs. A.A. Askhedkar Coordinator: Mrs. M.R. Ingle

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